Parity generation provides a simple means for detecting errors in both data recording and data transmission. A data quantity may be allocated a parity bit having a value which may be computed from the various bits of the data. A parity bit may be generated from the various bits of the data being read. The data can have even or odd parity and the parity bit will be responsible for making the data and parity bit be even or odd based on user input. The parity bit designates whether or not a transmitted character, or data packet, has arrived correctly. During parity checking, if the device is configured to always have even parity, the parity checking feature will indicate a parity error if odd parity is received. On existing first-in first-out (FIFO) buffers, the parity generation and checking circuitry may be located in the write data path of the integrated circuit or chip. As memory devices generally, and FIFO devices particularly, provide additional access speeds and more efficient real estate utilization, the parity generation and checking circuitry in the write data path can slow down the performance of the device.